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    • 专利摘要:
    A method of manufacturing a CMOS image sensor suitable for improving characteristics of a CMOS image sensor by improving charge transport efficiency and suppressing diffusion of thermally generated charges while having high photocharge generating efficiency for short wavelength light is disclosed. The present invention is an ion implantation for it is difficult to satisfy the shallow thickness of the low voltage current into the process during the formation of the pinned picture P 0 diffusion region of the diode is both a relatively high concentration forming conditions of P 0 diffusion region, one N 0 diffusion region forming After the source / drain ion implantation and annealing process of the transistor, ion implantation is performed to form a P 0 diffusion region in a state of being deposited to a TEOS film. Accordingly, the ion implantation can be performed at a high concentration during ion implantation for forming the P 0 diffusion region, and the P 0 diffusion region is formed thinly because the TEOS film plays a buffering role during ion implantation.
    公开号:KR20020052712A
    申请号:KR1020000082148
    申请日:2000-12-26
    公开日:2002-07-04
    发明作者:박재영；이주일
    申请人:박종섭；주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Method for fabricating low voltage pinned potodiode in CMOS image sensor
    [12] The present invention relates to a method for manufacturing a low voltage pinned potodiode applied to a complementary metal oxide semiconductor (CMOS) image sensor.
    [13] CCD (charge coupled device) has many disadvantages such as complicated driving method, high power consumption, high number of mask process steps, complicated process, and difficult to implement signal processing circuit in CCD chip. In order to overcome such drawbacks, the development of a CMOS image sensor using a sub-micron CMOS manufacturing technology has been studied in recent years. The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detects signals in a switching method, and implements an image by using a CMOS manufacturing technology, which consumes less power and uses 30 to 40 masks as many as 20 masks. Compared to CCD process that requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one chip, which is attracting attention as the next generation image sensor.
    [14] However, until now, since image quality is lower than that of CCD, efforts are being made to improve them. In other words, in the CMOS image sensor, the photodiode is an introduction part that converts incident light according to each wavelength into an electrical signal. Ideally, all the incident light has a quantum efficiency of 1 at all wavelengths. Because it's a collection, efforts are underway.
    [15] FIG. 1 is a circuit diagram of a typical unit pixel of a CMOS image sensor, and includes one photodiode (PD) and four NMOS transistors, and four transistors include a transfer gate (Tx), a reset gate (Rx), and a drive. It consists of the gate MD and the select gate Sx. Outside the unit pixel, a load transistor is formed to read an output signal.
    [16] FIG. 2 is a plan view showing a light sensing region, a field region, and a transfer gate Tx composed of a conventional low voltage pinned photodiode, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. 2. This is the case where the photodiode of the sensing area is composed of a P / N / P type pinned photodiode. Referring to FIG. 3, a P / N / P-type pinned photodiode is formed with a P- epitaxial layer 22 epitaxially grown on a P + substrate 21, and inside the P- epitaxial layer 22. An N − diffusion region 24 is formed, and a P 0 diffusion region 25 is formed above the N − diffusion region 24 and below the surface of the P- epi layer 22. Floating diffusion 26 is formed on the other end substrate of the transfer gate Tx.
    [17] When the N − diffusion region 24 and the P region (P 0 diffusion region, P-epi layer) of the low voltage pinned photodiode of the above structure are biased, the impurity concentrations of the N − diffusion region 24 and the P region are appropriately when formulated N - diffusion region 13 is fully depleted (fully depletion) presented as N - diffusion region (24) P- epitaxial layer 22 is present in the lower part and the N - diffusion region (24) P present on the upper As the depletion region extends to the zero diffusion region 25, more depletion layer expansion occurs to the P-epi layer 22 having a relatively low dopant concentration.
    [18] The voltage of the N - diffusion region 13 at this time is referred to as "pinning voltage". As described above, the pinned photodiode can secure a wide depletion region deep in the substrate, thereby generating and accumulating many photocharges with respect to light incident from the outside.
    [19] However, in the conventional low voltage pinned photodiode having such a structure, the P 0 diffusion region 25 should be doped with a relatively higher concentration of impurities than the N − diffusion region 24, and also formed shallow.
    [20] That is, the P 0 diffusion region 25 has a relatively high concentration in order to completely deplete the N − diffusion region 24 to increase the efficiency (charge transfer efficiency) in which photo generated charges are transported by floating diffusion. Should be The P 0 diffusion region 25 should be shallow in order to receive the blue signal, which is a short wavelength, in the low voltage pinned photodiode as much as possible.
    [21] However, current energy of the ion implantation equipment is limited to stably use up to 30KeV and it is very difficult to form the P 0 diffusion region 25 at a high concentration and shallow due to the diffusion of impurities by the thermal process.
    [22] In the present process, when the P 0 diffusion region 25 is made high, the N - diffusion region 24 is completely depleted, but impurities diffuse into the subsequent thermal process, so that the P 0 diffusion region 25 is formed on the silicon surface (epitaxial surface). Since it is difficult to receive the blue signal, and the side diffusion occurs, the P 0 diffusion region 25 acts as a barrier, thereby greatly reducing the charge transport efficiency.
    [23] In addition, when the P 0 diffusion region 25 is formed at a shallow and relatively low concentration with current equipment, the P 0 diffusion region 25 is first completely depleted, thereby generating thermal charges generated from dangling bonds on the silicon surface. Thermally generated charge is diffused into the N − diffusion region 24 to generate a noise phenomenon rather than pure photocharge.
    [24] In order to solve the above problems, the present invention has high photocharge generating efficiency for short wavelength light, improves charge transport efficiency, and suppresses diffusion of thermally generated charges, thereby improving characteristics of a CMOS image sensor. It is an object of the present invention to provide a method for manufacturing a CMOS image sensor suitable for
    [1] 1 is a circuit diagram of a conventional image sensor unit pixel;
    [2] 2 is a plan view in which a light sensing region and a transfer gate are laid out according to a conventional technique;
    [3] 3 is a cross-sectional view taken along line AA ′ of FIG. 2;
    [4] 4A to 4C are cross-sectional views showing a low voltage pinned photodiode manufacturing process according to a preferred embodiment of the present invention.
    [5] * Explanation of symbols for main parts of the drawings
    [6] 401: P + silicon substrate 402: P- epi layer
    [7] 403: field insulating film 404: gate electrode of transfer transistor
    [8] 405: N - ion implantation mask pattern 406: N - ion implantation region
    [9] 407: gate sidewall spacer 408: floating sensing junction
    [10] 409: TEOS film 410: P 0 ion implantation mask pattern
    [11] 411: P 0 ion implantation region
    [25] According to an aspect of the present invention, there is provided a CMOS image sensor manufacturing method comprising: forming a gate electrode of a transistor on a substrate of a first conductivity type; Forming a first ion implantation region of a second conductive type of a pinned photodiode in the substrate; Performing source / drain ion implantation and annealing of the transistor; Depositing an insulating film on the entire surface of the resultant material; And forming a second ion implantation region of a first conductivity type of the pinned photodiode between the substrate surface and the first ion implantation region.
    [26] The technical principle of the present invention having the above-described characteristic configuration is as follows. Since the low-voltage current of the process in the formation of the pinned picture P 0 diffusion region of the diode it is difficult to meet the relatively high concentration, yet shallow thickness of the forming conditions of the P 0 diffusion region, once subjected to an ion implantation for the N 0 diffusion region is formed, and then, After the source / drain ion implantation and annealing process of the transistor, ion implantation is performed to form the P 0 diffusion region in the state of being deposited to the TEOS film.
    [27] Accordingly, the ion implantation can be performed at a high concentration during ion implantation for forming the P 0 diffusion region, and the P 0 diffusion region is formed thinly because the TEOS film plays a buffering role during ion implantation. Therefore, the photoelectron generation efficiency is increased and the charge transport efficiency is improved by completely depleting the N − diffusion region. In addition, because of the high concentration, the charge generated in the dangling bond on the silicon surface can be prevented from penetrating into the N - diffusion region, thereby improving noise characteristics.
    [28] In addition, since it is formed with a shallow depth, it has high photocharge generating efficiency for short wavelength light, thereby improving the characteristics of the overall CMOS image sensor.
    [29] DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
    [30] 4A to 4C are cross-sectional views illustrating a process of manufacturing a pinned photodiode according to an exemplary embodiment of the present invention.
    [31] First, referring to FIG. 4A, a wafer in which a low concentration P- epi layer 402 is grown on a P + silicon substrate 401 is prepared, and then a field insulating layer 403 and a gate electrode 404 of a transfer transistor are formed. do. Subsequently, an N − ion implantation mask pattern 405 having an open active region where a photodiode is to be formed is formed, and then ion implantation is performed to form an N − ion implantation region in the P-epi layer 402 of the photodiode active region. 406 is formed. At this time, ion implantation uses P31 ions under an energy of about 180 KeV and a dose of about 2E12.
    [32] Thereafter, as illustrated in FIG. 4B, the N − ion implantation mask pattern 405 is removed and a series of processes such as the gate sidewall spacer 407 and the source / drain ion implantation and annealing of the transistor are performed. In the figure only the floating sensing junction (FD) 408 formed by the process is shown.
    [33] Subsequently, as shown in FIG. 4C, a TEOS film 409 is formed on the entire surface of the resultant, about 800-1200 이온, and then a P 0 ion implantation mask pattern 410 is formed. The P 0 ion implantation region 411 is formed under the surface of the P- epi layer 402 by implantation. At this time, the ion implantation uses BF2 ions under an energy of about 30 KeV and a dose condition of about 6E12-7E12, in which an important point is that the dose is larger than that of the conventional 5E12, and the P 0 ion implantation region 411 is used. Is formed at a relatively higher concentration than the prior art.
    [34] In the present embodiment, the TEOS film 409 is applied. The TEOS film 409 is used as a kind of pre-insulating metal film (PMD) during the CMOS image sensor process. Without further processing, only the process sequence and ion implantation conditions need to be adjusted. Of course, other insulating films other than TEOS films are applicable.
    [35] Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
    [36] The present invention enables formation of a high concentration and shallow P 0 ion implantation region when forming a low voltage pinned photodiode, thereby improving the characteristics of a CMOS image sensor having such a low voltage pinned photodiode.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] In the CMOS image sensor manufacturing method,
    Forming a gate electrode of a transistor on a substrate of a first conductivity type;
    Forming a first ion implantation region of a second conductive type of a pinned photodiode in the substrate;
    Performing source / drain ion implantation and annealing of the transistor;
    Depositing an insulating film on the entire surface of the resultant material; And
    Forming a second ion implantation region of a first conductive type of a pinned photodiode between the substrate surface and the first ion implantation region
    CMOS image sensor manufacturing method comprising a.
    [2" claim-type="Currently amended] The method of claim 1,
    The insulating film is a CMOS image sensor manufacturing method characterized in that the TEOS film.
    [3" claim-type="Currently amended] The method of claim 2,
    The CMOS image sensor manufacturing method characterized in that for forming the TEOS film about 800-1200 800.
    [4" claim-type="Currently amended] The method of claim 3,
    And the second ion implantation region is formed by ion implantation of BF2 ions under an energy of about 30 KeV and a dose condition of about 6E12-7E12.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-12-26|Application filed by 박종섭, 주식회사 하이닉스반도체
    2000-12-26|Priority to KR1020000082148A
    2002-07-04|Publication of KR20020052712A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000082148A|KR20020052712A|2000-12-26|2000-12-26|Method for fabricating low voltage pinned potodiode in CMOS image sensor|
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